This demonstrates some of the aspects of pipelining in computer design and programming.
This applet was originally written by Michael Chamberlain and John Elmore for class EE3833. The class was taught by Stephen P. DeWeerth of Georgia Institute of Technology. Several modifications were added by Curt Hill.
There are several types of instructions for the MIPS processors. The R type has one destination registers and two source registers for operands. (A register is preceded by a $ sign so register zero is denoted by $0.) The I type has two registers and an immediate instruction. The M type operations have a register followed by an immediate offset and base register. The Branch instructions have two registers and an immediate operand. Register zero always retains a zero and cannot be stored into.
The following table shows some of the instructions that are available for this computer:
| Mnemonic | Type | Operand 1 | Operand 2 | Operand 3 | Description |
|---|---|---|---|---|---|
| ADD | R | Dest | Source1 | Source2 | Add value addressed by the two source operands to the dest
operand. Add $3 $2 $1 - Source address is sum of register 2 and 1 and placed in register 3. |
| ADDI | I | Dest | Source | Immediate | Add value addressed by the two source operands to the dest
operand. Add $1 $2 20 - Add 20 to the contents of register 2 and place in register 1. |
| BEQ | I | First Source reg. | Second Source reg. | Immediate offset value | Compare the first two registers and move the immediate to the Program
Counter, if equal. BEQ $5 $2 10 - Compare registers 5 and 2 and branch to location 10 if they are equal. |
| BNE | I | First Source reg. | Second Source reg. | Immediate offset value | Compare the first two registers and move the immediate to the Program
Counter, if not equal. BNE $5 $2 10 - Compare registers 5 and 2 and branch to location 10 if they are not equal. |
| LW | M | Dest. reg. | Offset | (Base reg.) | Load the destination register with the memory value computed by the
sum of the offset and the base register. LW $1 15($2) - Add 15 to register 2 to compute the memory location to load into register 1. |
| MULT | R | Dest | Source1 | Source2 | Multiply the two source register contents and place the results in the
destination register. Add $6 $2 $7 - Multiply contents of registers 2 and 7 and store results in register 6. |
| NOP | No operation. Sometimes placed in code to hold a location. | ||||
| SUBI | I | Dest | Source | Immediate | Destination register receives the immediate subtracted from the source
register. SUBI $1 $2 20 - Subtract 20 from the contents of register 2 and place in register 1. |
| SW | M | Source reg. | Offset | (Base reg.) | Save the value in the first operand into the memory address computed
by the sum of the offset and the base register. SW $1 25($2) - Store the contents of register 1 in the memory location whose address is the sum of 25 and register 2. |
Any of these instructions may be followed by a semicolon(;) and then comments.
Instruction - Shows the memory that contains instructions. Each line
contains an address and the instruction. In an actual machine each instruction
would occupy several memory cells and the contents would always be numeric.
Memory - The data memory. Each line contains an address and the
contents of that memory cell. In an actual machine the data and instructions
would be in the same memory.
Register file - The 32 registers of the
machine. Each line specifies the register number and contents. Register 0 cannot
be changed. A register is specified by preceding the register number with a $
when forming an instruction.
Messages - The explanatory messages
produced by the simulator. These may be errors about the use of the simulator or
format of the instructions. They may also indicate the actions of the pipeline
stages.
Stages - The MIPS pipeline has five stages: Fetch, Decode, Execute,
Memory and Write Back. Each shows the address of the instruction they are
working on and other pertinant information.
Instructions - The number
of instructions that have been completed.
Cycles - The number of
steps that have been performed.
CPI - Cycles Per Instruction. The
average number of cycles per completed instruction. The smaller this value the
better the program was able to take advantage of the pipeline parallelism.
Reset - Clears messages, registers, pipeline stages and data memory.
This suspends any execution in progress, but does not clear the instructions.
Clear instructions - Clears everything. Similar to Reset but it also
clears the instructions.
Help - Opens a new window with a summary of
instructions that is not as detailed as the above.
Step - Advances
the processing of every stage by one step. This is not the same as a single step
on most simulators since it does not accomplish an entire instruction.
Delete Instruction - Deletes the highlighted instruction from the
Instruction pane and moves following ones up. An instruction must be
highlighted.
Run - Executes N steps, where N is obtained from the
text field immediately to the right of the button. Run 1 is the same as Step. If
the field is empty or less than one an error is displayed. If the number is
larger than the number of steps needed to complete the program the program will
terminate when the first non-instruction is executed.
Add Instruction
- Adds one instruction after checking it to the end of the program being built
in the Instruction pane. The field to the right of the button contains the
instruction to be added. If the instruction is incorrect a message is displayed
in the Message pane.
Change Instruction - Replace the instruction
highlighted in the Instruction pane with the instruction that is in the field
immediately to the right. The instruction is checked in a way similar to the Add
Instruction button.
The Java source in a zip file.
Return to the simulators page.
Last time updated this page: September 7, 2007